Galinstan Nanocavity Data Storage puts a liquid metal alloy inside an engineered nanocavity and reads the state of the oxide that forms on it. The appeal is that the storage primitive is a material property rather than a transistor, so density is set by how small a cavity can be made rather than by a process node.
Confine galinstan in a nanocavity and a gallium-oxide skin forms at the interface. That skin has distinguishable conductance states, and the current model treats the switching as oxide-vacancy behaviour rather than as a bulk phase change — which matters, because the two mechanisms imply completely different endurance and retention physics.
A note on naming: the designator is GNDS. “GNSD” appears in some older material and is a spelling drift, not a second technology.
A storage device in its own right rather than a subsystem of anything larger. Freed from that context, the bit mechanism becomes an open question rather than a given, and two candidates are under active comparison: gallium-filament conductive-bridge switching, and ferroelectric hafnium-zirconium oxide. They are genuinely different physics with different failure modes, and the line has not committed to either.
The product of a deliberate reset. Rather than encoding a bit in an oxide state at all, WIRE encodes it in the fill state of a galinstan nanopore — the configuration of the metal in the pore is the value. It was invented as a clean-slate alternative precisely because the earlier models had accumulated mechanism-level disagreements, and it is easier to design a new thing honestly than to keep patching one whose physics you no longer trust.
The archival fork, and the cleanest experiment of the set. A credit-card footprint holding roughly 52 TB across some 2.6 × 10¹⁴ cells — each about 20 nm pitch, a 14 nm mouth narrowing to a 4 nm throat, 50 nm deep, with a 2 nm gallium-oxide skin whose conductance window spans about 100×, binned into five levels for 2.25 bits per cell. Being write-once removes the endurance problem entirely, which leaves exactly one question standing.
Two tracks, deliberately sequenced so that the physics can be tested before the manufacturing is solved. The first uses something you can order; the second is the one that matters long-term.
Anodic alumina membranes bought off the shelf. Pore geometry is not ideal and the material is not the target substrate, but it lets the bit mechanism be tested without waiting on process development. This is the route to a first real measurement.
Imprint, cure, fire, then seal by atomic layer deposition. The real route, using the laboratory’s own substrate chemistry, where pore geometry becomes a design variable rather than a constraint accepted from a supplier.
Mechanism-level mismatches exist between the v1.0 and v2.0 descriptions of how the cell works. That is stated rather than smoothed over, and it is a large part of why the emphasis is on getting to a physical measurement rather than refining the simulation further.